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7
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Quiz of Combinational Circuit (1~8)
8. Combinational Circuit Design(Simulation
& Lab)
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HomeWorks: 5.9, 5.10, 5.34, 7.27, 7.37,
8.3, 8.9 (Due:8/Nov)
Problems for Next Lab.: 8.A, 8.M
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10
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10. Introduction
to VHDL
Lab. for counters and timing simulation
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Reference for Mid-Exam: 9.8,
9.18-9.21, 9.25, 9.28, 9.29, 10.15~10.18
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16
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13. Clocked Sequential Circuits
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期末小組討論規則：
1. 期中考70分以上者可不參加(請先向助教登記)
2. 召集人期末考加10分(至少需討論兩次)。
3. 參加者期末考成績=70%*個人成績+30%*團體成績
4.
未參與討論者，團體成績以零分記，其個人成績不列入團體成績
The groups are
reorganized as followed(The 1st person is the leader):
Group1: 張英麒; 黃冠樺; 林佑威; 吳昱賢; 李佩芬; 楊岳霖; 陳東傑;
Group2: 杜建德; 楊繕逢; 曹印吾; 洪崇瑋; ;許景貴; 曾韋哲; 李庚翰;
Group3: 黃姿瑋; 鄭又嘉; 張熒珊; 葉立誠; 劉晏君;
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18
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Final Exam
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Project:
1.
Demostration & Oral
Test Date: 20/Jan 09:00 ~ 17:00，prepare the design document (schematic or VHDL or any
draft to prove that you design it yourself)
2.
You can use existing
components to design (e.g. 7474、7473、74163、74161、7-segment
decoders)
3. Design with VHDL is a plus.(Refer
chapter 17)
Reference for Final-Exam(New Version):
11.9, 11.10, 11.17~11.19,
12.4, 12.10, 12.17, 12.21, 12.22,
13.7, 13.8, 13.17,
14.12, 14,14, 14.17, 14.18
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