Digital System Design 
TextBook: 
　

Charles H. Roth, Jr. "Fundamentals of Logic Design", 5th ed. Thomson Brooks/Cole.

 攝於北大武山

  
Course Schedule :
IMI-023A

Lecture

 		Mini-Quiz

Homework
Sep/21

1. Number System and Conversion

2. Boolean Algebra

     1.10, 1.18, 1.24, 1.25, 1.27

   2.18, 2.20, 2.21       Due:2005/Oct/12

Sep/28

3. Boolean Algebra

4. Minterm and Maxterm Expansions(4.1~4.6)

      3.19, 3.20, 3.26

   4.5, 4.6, 4.9, 4.10    Due:2005/Oct/12

      Solution

Oct/05

4. Minterm and Maxterm Expansions(4.7)

5. Karnaugh Maps

   4.26, 4.32

5.27, 5.29, 5.30   Due:2005/Oct/21

Oct/12

7. NAND and NOR Gates & Lab

　

     7.29, 7.38, 7.39

8.A, 8.M

Due:2005/Oct/22

Oct/19

Lab

　

　

   

Oct/26

8. Combinational Circuit Design

9. Mux, Decoders and PLD

 		    8.3, 8.6, 8.8

9.8, 9.15, 9.23, 9.26

Due:2005/Nov/1

Nov/02

9. Mux, Decoders and PLD　

11. Latches and Flip-Flops

　

 		  

Novr/09

12. Registers and Counters

　

 		    　  

Nov/16

Mid-Term Exam. (LAB)

   

Nov/23

 		LAB presentation    

Nov/30

　

10. Introduction to VHDL

    

Dec/07

 		13. Clocked Sequential Circuits

　

 

　

Due:2005/Dec/12

Dec/14

Introduction to  Very-Simple-CPU

14. State Graphs and Tables

　

 		Reference:

CPU Design

Homework: 

Part I:  13.13, 13.17 (EveryOne)

Part II: Write a design report of VerySimpleCPU as section 2 and    section 3 of CPU_Design reference. (Every Team)

　

　

Dec/21

17. VHDL for Sequential Logic

 		   
Dec/28 15. State Assignments

16. Sequential Circuit Design

   

Jan/04

18. Circuits for Arithmetic   Operations

 		   

Jan/11

 		19. State machine Design with SM Charts    

Jan/18

Final Exam(LAB)

 		   

　  
TA: 

 林竺玄

　

Grading 

üMid-term exam. 30%

üFinal-term exam 40%

üQuestion-raising  10%

üHome Work 20%